Wesley Holland

SoC Architect

I live in San Diego and work at Qualcomm designing next-generation SoCs.


Research Interests

  • Deep Learning
  • Computer Vision
  • Virtual / Augmented Reality
  • Computational Photography
  • Computer Architecture
  • System-On-Chip Design


  • Technical leadership: developing strategy in alignment with business goals, project planning, managing teams and technical forums to drive technical consensus and on-time execution
  • Imaging expertise: image signal processing, computer vision, algorithm development in various languages/frameworks (C/C++, Python, Matlab, Octave, Java, Halide, OpenVX, OpenCV), image quality evaluation (DxOMark, imatest), camera sensor technology (stereo, depth, Intel RealSense, TOF, Always-On, PDAF, HDR, global shutter, non-Bayer), MIPI camera interface specifications (D-PHY, CPHY, CSI2/3, DSI) and associated digital controllers and analog PHYs, and overall industry landscape
  • Deep learning expertise: designing and training deep learning models (CNNs, LSTMs, GRUs, Seq2Seq, attention, GANs, Transformers) using open source software frameworks (Caffe, TensorFlow, Keras, PyTorch, NumPy, Pandas, scikit-learn), with extensive expertise in efficient on-device mobile / edge inference for computational photography (super-resolution, beautification, noise reduction) and computer vision (depth estimation, object detection / tracking)
  • Architectural knowledge: digital signal processors, accelerators / co-processors, 3D graphics, video encode/decode, x86, ARM, content protection, security, caching and coherency, compression, pipelining, branch prediction, virtual memory, on-chip bus / NOCs, memory arbitration, memory controllers, and power/performance analysis


San Diego, CA
Principal Engineer
  • Drove hardware / software development for emerging computer vision and machine learning use cases on Qualcomm Snapdragon SoCs, including video noise reduction, video super-resolution, photo beautification, semantic segmentation, time/space warp for virtual reality, chromatic aberration correction, object detection/recognition/tracking, 6DOF / SLAM positional tracking, eye-tracking for foveated rendering, and others
  • Led cross-org working groups driving imaging and computer vision system architecture spanning multiple Qualcomm hardware IPs, hardware/software strategy and planning, use case decomposition, and competitive analysis across tiers and segments
Intel Corporation
Austin, TX
SoC Architect
  • Drove Intel’s roadmap for camera and computer vision hardware as lead imaging architect for 22nm and 14nm SoCs, including the Atom Z35xx/Z37xx/E38xx/Z83xx/Z85xx/Z87xx, the Celeron J17xx/J18xx/J19xx/N28xx/N29xx, and the Pentium J28xx/J29xx/N35xx
  • Developed SoC landing zone requirements for camera and computer vision hardware and software in collaboration with OEMs, industry experts, standards organizations, and algorithm researchers
  • Authored platform and SoC architecture specifications for camera and computer vision hardware, including CSI controllers, DPHY/CPHY analog blocks, Bayer noise reduction, phase-detect auto-focus (PDAF) pixel processing, video HDR (VHDR) tone mapping, defect pixel correction, demosaic, luma/chroma noise reduction, up-/down-scaling, programmable SIMD image signal processors, geometric distortion correction, digital video stabilization, convolutional neural network (CNN) accelerators, feature extraction blocks (FAST9, SIFT, etc.), and others
  • Led cross-org/cross-geo working groups and virtual teams consisting of dozens of contributors, driving imaging-related hardware/software execution to ensure complete solutions, providing customer training and support, performing benchmarking and competitive analysis, and collaboratively debugging silicon issues
Intel Corporation
Austin, TX
Component Design Engineer
  • Owned micro-architecture and front-end design in multimedia cluster for Intel's 45nm, 32nm, and 22nm low-power Atom-based SoCs, including the Intel Atom Z25xx/Z27xx/Z34xx; responsible for compute blocks (raster/de-raster, distortion correction, noise reduction, demosaic, etc.), MIPI CSI/DSI controllers, bus-translation logic, memory arbitration systems, DMA engines, SRAM ECC logic, AES encryption/decryption, and integration of various 3rd-party graphics and video IP
  • Drove designs through tape-out and post-silicon, incorporating design-for-test logic (scan, BIST), crafting testbenches, writing test content, running simulations, synthesizing logic, running gate-level simulation, driving timing closure, cleaning up DRC violations, and handling netlist ECOs
  • Led technical tasks, trail-blazing SoC tool/methodology flows, driving cross-project initiatives for design best-practices, organizing international face-to-face meetings (both internal and with external IP vendors and industry partners), and driving post-silicon debug task forces
MSU Electrical and Computer Engineering Department
Starkville, MS
Research / Teaching Assistant
  • Researched digital design automation strategies
  • Developed prototype high-level language to Verilog synthesis tool
  • Taught logic devices and digital design
Institute for Signal and Information Processing
Starkville, MS
Research Assistant
  • Researched machine-learning techniques for speech recognition
  • Developed grammar specification conversion tools for mobile speech recognition


Mississippi State University
Starkville, MS
Doctor of Philosophy in Electrical and Computer Engineering (In Progress)
University of Texas
Austin, TX
Doctoral coursework in Electrical Engineering (Withdrawn in Good Standing)
Mississippi State University
Starkville, MS
Master of Science in Computer Engineering
Mississippi State University
Starkville, MS
Bachelor of Science in Computer Engineering


  • A. Turner, G. Patsilaras, B. Rychlik, W. Holland, J. Shabel, S. Booth, "SYSTEM AND METHOD FOR MIXED TILE-AWARE AND TILE-UNAWARE TRAFFIC THROUGH A TILE-BASED ADDRESS APERTURE," United States Patent 11,016,898, May. 25, 2021.
  • W. Holland, "DEFINE A PRIORITY OF MEMORY TRAFFIC BASED ON IMAGE SENSOR METADATA," United States Patent 10,841,451, Nov. 17, 2020.
  • W. Holland, B. Rychlik, A. Turner, G. Patsilaras, J. Shabel, S. Booth, "SYSTEM AND METHOD FOR INTELLIGENT TILE-BASED PREFETCHING OF IMAGE FRAMES IN A SYSTEM ON A CHIP," United States Patent 10,747,671, Aug. 18, 2020.
  • M. Varia, S. Gadelrab, W. Holland, J. Cheung, D. Backer, T. Longo, "SYSTEM AND METHOD FOR FOVEATED COMPRESSION OF IMAGE FRAMES IN A SYSTEM ON A CHIP," United States Patent 10,511,842, Dec. 16, 2019.
  • B. Rychlik, W. Holland, H. Liu, A. Turner, "CACHE COHERENCE WITH FUNCTIONAL ADDRESS APERTURES," United States Patent 10,503,842, Dec. 09, 2019.
  • K. Anderson, W. Holland, "LAST-LEVEL PROJECTION METHOD AND APPARATUS FOR VIRTUAL AND AUGMENTED REALITY," United States Patent 10,445,922, Oct. 15, 2019.


  • W. Holland, Q. Du, “Adversarially Regularized Autoencoder for Hyperspectral Image Unmixing,” SPIE Remote Sensing, Digital Forum, 2020.
  • W. Holland, Y. Dandass, “Optimizing Pipelining in HDL Generated Automatically from C Source Codes,” Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, 2008.
  • W. Holland, “A framework for automatically generating optimized digital designs from C language loops,” M.S. thesis, Mississippi State University, Starkville, MS, 2008.
  • W. Holland, D. May, J. Baca, G. Lazarou and J. Picone, "A Unified Language Model Architecture for Web-based Speech Recognition Grammars," IEEE International Symposium on Signal Processing and Information Technology, Vancouver, Canada, 2006.
  • W. Holland, J. Baca, D. Duncan, and J. Picone, "Language Model Grammar Conversion," 2006 World Congress in Computer Science, Computer Engineering and Applied Computing, Las Vegas, Nevada, USA, 2006.


  • National Science Foundation Graduate Research Fellow
  • Barry M. Goldwater Scholar
  • Bagley College of Engineering Student Hall of Fame
  • Bagley College of Engineering "Most Outstanding Computer Engineering Senior"
  • Mississippi State University Student Hall of Fame
  • National Merit Scholar


  • English (native-speaker)
  • Spanish (SIELE B1 level)
  • Mandarin Chinese (HSK 1 level)