Wesley Holland

SoC Architect

I'm Wesley Holland. I live in Austin, TX. I work at Intel Corporation designing next-generation Intel Atom-powered SoCs for ultra-mobile applications like wearables, smartphones, and tablets.


  • Technical leadership: experience managing teams and forums to drive technical tasks to completion; familiarity with project management, agile development, Scrum project ownership, and JAMA
  • Imaging expertise: extensive experience with image signal processing, computer vision, deep learning, imaging software frameworks (Halide, OpenVX, OpenCV, Caffe, TensorFlow), image quality evaluation (DxOMark, imatest), camera sensors technology (stereo, depth, Intel RealSense, PDAF, HDR, global shutter, non-Bayer), MIPI camera interface specifications (D-PHY, CPHY, CSI2/3, DSI) and associated digital controllers and analog PHYs, and the overall industry landscape for imaging
  • Broad architectural knowledge: 3D graphics, video encode/decode, x86, content protection, security, caching and coherency, pipelining, branch prediction, virtual memory, on-chip bus protocols (AHB, APB, AXI, OCP), memory arbitration, memory controllers, and power/performance
  • Extensive SoC design experience: micro-architecture, RTL/HDL languages/tools (Verilog, System Verilog, VHDL, System C, Synopsys VCS, Synopsys Design Compiler, Verdi, Cadence NCSIM, Spyglass), synthesis, logic/memory BIST insertion, scan, formal verification, floorplanning, place-and-route, static timing analysis, gate-level simulation, netlist ECOs, and post-silicon debug


Intel Corporation
Austin, TX
SoC Architect
  • Served as lead imaging architect, driving Intel’s roadmap for camera and computer vision hardware for 22nm and 14nm SoCs, including the Atom Z35xx/Z37xx/E38xx/Z83xx/Z85xx/Z87xx, the Celeron J17xx/J18xx/J19xx/N28xx/N29xx, and the Pentium J28xx/J29xx/N35xx
  • Collaborated with OEMs, industry experts, standards organizations, algorithm researchers, and platform teams to drive architectural strategy and develop SoC landing zone requirements for camera and computer vision hardware and software
  • Authored high-level platform and SoC architecture specifications for camera and computer vision hardware, including CSI controllers, DPHY/CPHY analog blocks, bayer noise reduction, phase-detect auto-focus (PDAF) pixel processing, video HDR (VHDR) tone mapping, defect pixel correction, demosaic, luma/chroma noise reduction, up-/down-scaling, programmable SIMD image signal processors, geometric distortion correction, digital video stabilization, convolutional neural network (CNN) accelerators, feature extraction blocks (FAST9, SIFT, etc.), and others
  • Led cross-org/cross-geo working groups and virtual teams consisting of dozens of contributors, driving imaging-related hardware/software execution to ensure complete solutions, providing customer training and support, performing benchmarking and competitive analysis, and collaboratively debugging silicon issues
Intel Corporation
Austin, TX
Component Design Engineer
  • Worked on design team for Intel's 45nm, 32nm, and 22nm low-power Atom-based SoCs, including the Intel Atom Z25xx/Z27xx/Z34xx
  • Owned micro-architecture and design in multimedia cluster, responsible for compute blocks (raster/de-raster, distortion correction, noise reduction, demosaic, etc.), MIPI CSI/DSI controllers, bus-translation logic, memory arbitration systems, DMA engines, SRAM ECC logic, AES encryption/decryption, and integration of various 3rd-party graphics and video IP
  • Drove designs through tape-out, incorporating design-for-test logic (scan, BIST), crafting testbenches, writing test content, running simulations, synthesizing logic, running gate-level simulation, driving timing closure, cleaning up DRC violations, and handling netlist ECOs
  • Served as technical lead for many tasks, trail-blazing SoC tool/methodology flows, driving cross-project initiatives for design best-practices, organizing international face-to-face meetings (both internal and with external IP vendors and industry partners), and driving post-silicon debug task forces
MSU Electrical and Computer Engineering Department
Starkville, MS
Research / Teaching Assistant
  • Researched digital design automation strategies
  • Developed prototype high-level language to Verilog synthesis tool
  • Taught logic devices and digital design
Institute for Signal and Information Processing
Starkville, MS
Research Assistant
  • Researched machine-learning techniques for speech recognition
  • Developed grammar specification conversion tools for mobile speech recognition


University of Texas
Austin, TX
18 hours doctoral coursework - Withdrawn in Good Standing
Mississippi State University
Starkville, MS
Master of Science in Computer Engineering (4.0 GPA)
Mississippi State University
Starkville, MS
Bachelor of Science in Computer Engineering (4.0 GPA)


  • W. Holland and Y. Dandass, “Optimizing Pipelining in HDL Generated Automatically from C Source Codes,” Engineering of Reconfigurable Systems and Algorithms, Las Vegas, Nevada, USA, 2008.
  • W. Holland, “A framework for automatically generating optimized digital designs from C language loops,” M.S. thesis, Mississippi State University, Starkville, MS, 2008.
  • W. Holland, D. May, J. Baca, G. Lazarou and J. Picone, "A Unified Language Model Architecture for Web-based Speech Recognition Grammars," IEEE International Symposium on Signal Processing and Information Technology, Vancouver, Canada, 2006.
  • W. Holland, J. Baca, D. Duncan, and J. Picone, "Language Model Grammar Conversion," 2006 World Congress in Computer Science, Computer Engineering and Applied Computing, Las Vegas, Nevada, USA, 2006.


  • National Science Foundation Graduate Research Fellowship
  • Barry M. Goldwater Scholarship
  • Bagley College of Engineering Student Hall of Fame
  • Bagley College of Engineering "Most Outstanding Computer Engineering Senior"
  • MSU Student Hall of Fame
  • National Merit Scholarship


  • I.E.E.E. (member since 2005)
  • A.C.M. (member since 2005)

Relevant Coursework

  • Electronic Circuit Design
  • Digital System Design
  • Embedded Systems
  • Computer Architecture
  • Network Processor Architectures
  • Modern Processor Design
  • Introduction to VLSI Design
  • VLSI Systems
  • VLSI Design II
  • Analog Integrated Circuit Design
  • Application-Specific Processing
  • Mixed-Signal System Design and Modeling
  • System-On-Chip Design
  • Neural Networks